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CY62136ESL MoBL
2 Mbit (128K x 16) Static RAM
Features

Very high speed: 45 ns Wide voltage range: 2.2 V to 3.6 V and 4.5 V to 5.5 V Ultra low standby power Typical standby current: 1 A Maximum standby current: 7 A Ultra low active power Typical active current: 2 mA at f = 1 MHz Easy memory expansion with CE and OE features Automatic power-down when deselected Complementary metal oxide semiconductor (CMOS) for optimum speed and power Available in Pb-free 44-pin thin small outline package (TSOP) II package
applications such as cellular telephones. The device also has an automatic power down feature that reduces power consumption when addresses are not toggling. Placing the device into standby mode reduces power consumption by more than 99% when deselected (CE HIGH). The input and output pins (I/O0 through I/O15) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH) or during a write operation (CE LOW and WE LOW). To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7) is written into the location specified on the address pins (A0 through A16). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A16). To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory appears on I/O8 to I/O15. See the "Truth Table" on page 11 for a complete description of read and write modes. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.

Functional Description
The CY62136ESL is a high performance CMOS static RAM organized as 128K words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life (MoBL) in portable
Logic Block Diagram
DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
ROW DECODER
128K x 16 RAM Array
SENSE AMPS
I/O0-I/O7 I/O8-I/O15
COLUMN DECODER BHE WE CE OE BLE
A11 A12
Cypress Semiconductor Corporation Document #: 001-48147 Rev. *C
*
198 Champion Court
A13 A14 A15 A16
*
San Jose, CA 95134-1709 * 408-943-2600 Revised January 03, 2011
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Contents
Pin Configuration ............................................................... 3 Product Portfolio ................................................................ 3 Maximum Ratings ............................................................... 4 Operating Range ................................................................. 4 Electrical Characteristics ................................................... 4 Thermal Resistance ............................................................ 5 Capacitance. ....................................................................... 5 Data Retention Characteristics ......................................... 6 Data Retention Waveform .................................................. 6 Switching Characteristics .................................................. 7 Switching Waveforms ........................................................ 8 Truth Table ........................................................................ 11 Ordering Information ....................................................... 12 Ordering Code Definition ............................................. 12 Package Diagram ............................................................. 13 Acronyms .......................................................................... 13 Document Conventions ................................................... 13 Units of Measure ......................................................... 13 Document History Page ................................................... 14 Sales, Solutions, and Legal Information ........................ 15 Worldwide Sales and Design Support ......................... 15 Products ...................................................................... 15 PSoC Solutions ........................................................... 15
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Pin Configuration
Figure 1. 44-Pin TSOP II (Top View) [1]
A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC
Product Portfolio
Power Dissipation Product Range VCC Range (V) [2] Speed (ns) Operating ICC, (mA) f = 1MHz Typ CY62136ESL Industrial 2.2 V to 3.6 V and 4.5 V to 5.5 V 45 2
[3]
f = fmax Typ [3] 15 Max 20
Standby, ISB2 (A) Typ [3] 1 Max 7
Max 2.5
Notes 1. NC pins are not connected on the die. 2. Datasheet specifications are not guaranteed for VCC in the range of 3.6 V to 4.5 V 3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 3V, and VCC = 5V, TA = 25 C
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Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature................................. -65 C to +150 C Ambient temperature with power applied ........................................... -55 C to +125 C Supply voltage to ground potential .................-0.5 V to 6.0 V DC voltage applied to outputs in High-Z State[4, 5] ...........................................-0.5 V to 6.0 V DC input voltage[4, 5] ........................................-0.5 V to 6.0 V Output current into outputs (LOW) .............................. 20 mA Static discharge voltage............................................ >2001 V (MIL-STD-883, Method 3015)Latch up current ....... >200 mA
Operating Range
Device CY62136ESL Range Industrial Ambient Temperature -40 C to +8 5C VCC[6] 2.2 V-3.6 V, and 4.5 V-5.5 V
Electrical Characteristics
Over the Operating Range 45 ns Parameter VOH Description Output HIGH voltage 2.2 < VCC < 2.7 2.7 < VCC < 3.6 4.5 < VCC < 5.5 VOL Output LOW voltage 2.2 < VCC < 2.7 2.7 < VCC < 3.6 4.5 < VCC < 5.5 VIH Input HIGH voltage 2.2 < VCC < 2.7 2.7 < VCC < 3.6 4.5 < VCC < 5.5 VIL Input LOW voltage 2.2 < VCC < 2.7 2.7 < VCC < 3.6 4.5 < VCC < 5.5 IIX IOZ ICC ISB1[8] Input leakage current VCC Operating supply current GND < VI < VCC f = fmax = 1/tRC f = 1 MHz VCC = VCCmax IOUT = 0 mA, CMOS levels Output leakage current GND < VO < VCC, Output disabled Test Conditions IOH = -0.1 mA IOH = -1.0 mA IOH = -1.0 mA IOL = 0.1 mA IOL = 2.1 mA IOL = 2.1 mA Min 2.0 2.4 2.4 - - - 1.8 2.2 2.2 -0.3 -0.3 -0.5 -1 -1 - - - Typ [7] - - - - - - - - - - - - - - 15 2 1 Max - - - 0.4 0.4 0.4 VCC + 0.3 VCC + 0.3 VCC + 0.5 0.6 0.8 0.8 +1 +1 20 2.5 7 A A A mA V V V Unit V
ISB2[8]
Automatic CE CE > VCC 0.2 V, VIN > VCC - 0.2 V or VIN < 0.2 V, power-down current -- f = fmax (Address and data only), CMOS inputs f = 0 (OE, BHE, BLE and WE), VCC = VCC(max) Automatic CE CE > VCC - 0.2 V, VIN > VCC - 0.2 V or VIN < 0.2 V, power-down current -- f = 0, VCC = VCC(max) CMOS inputs
-
1
7
A
Notes 4. VIL(min) = -2.0 V for pulse durations less than 20 ns. 5. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns 6. Full Device AC operation assumes a 100 s ramp time from 0 to VCC (min) and 200 s wait time after VCC stabilization. 7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 3 V, and VCC = 5V, TA = 25 C. 8. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
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Capacitance.
Parameter[9] CIN COUT Description Input capacitance Output capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = VCC(typ) Max 10 10 Unit pF pF
Thermal Resistance
Parameter[9] JA JC Description Thermal resistance (Junction to ambient) Thermal resistance (Junction to case) Figure 2. AC Test Loads and Waveforms
VCC OUTPUT R1 VCC R2 10% GND Rise Time = 1 V/ns Equivalent to: ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns
Test Conditions Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board
TSOP II 77 13
Unit C / W C / W
30 pF INCLUDING JIG AND SCOPE
THEVENIN EQUIVALENT RTH OUTPUT V TH
Parameters R1 R2 RTH VTH
2.5 V 16667 15385 8000 1.20
3.0 V 1103 1554 645 1.75
5.0 V 1800 990 639 1.77
Unit V
Note 9. Tested
initially and after any design or process changes that may affect these parameters
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Data Retention Characteristics
Over the Operating Range Parameter VDR ICCDR[11] tCDR [12] tR [13] Description VCC for data retention Data retention current Chip deselect to data retention time Operation recovery time CE > VCC - 0.2 V, VIN > VCC - 0.2 V or VIN < 0.2 V VCC = 1.0 V Conditions Min 1.0 - 0 45 Typ[10] - 0.8 - - Max - 3 - - Unit V A ns ns
Data Retention Waveform
Figure 3. Data Retention Waveform
DATA RETENTION MODE VCC CE
VCC(min)
tCDR
VDR > 1.0 V
VCC(min)
tR
Notes 10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 C 11. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR specification. Other inputs can be left floating 12. Tested initially and after any design or process changes that may affect these parameters 13. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s
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Switching Characteristics
Over the Operating Range Parameter[14,15] Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write Cycle[18] tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE Write cycle time CE LOW to write end Address setup to write end Address hold from write end Address setup to write start WE pulse width BLE/BHE LOW to write end Data setup to write end Data hold from write end WE LOW to High Z WE HIGH to Low Z
[16, 17] [16]
Description
45 ns Min 45 - 10 - - 5 - 10 - 0 - - 5 - 45 35 35 0 0 35 35 25 0 - 10 Max - 45 - 45 22 - 18 - 18 - 45 22 - 18 - - - - - - - - - 18 -
Unit
Read cycle time Address to data valid Data hold from address change CE LOW to data valid OE LOW to data valid OE LOW to Low Z
[16]
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
OE HIGH to High Z[16, 17] CE LOW to Low Z[16] CE HIGH to High Z
[16, 17]
CE LOW to power-up CE HIGH to ower-down BLE/BHE LOW to data valid BLE/BHE LOW to Low Z
[16] [16, 17]
BLE/BHE HIGH to High Z
Notes 14. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3 V, and output loading of the specified IOL/IOH as shown in the AC Test Loads and Waveforms on page 5 15. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification 16. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device 17. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 18. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
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Switching Waveforms
Figure 4. Read Cycle No.1: Address Transition Controlled [19, 20]
tRC RC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Figure 5. Read Cycle No. 2: OE Controlled [20, 21]
ADDRESS
tRC CE tACE OE tDOE BHE/BLE tLZOE tHZBE tDBE tLZBE DATA OUT HIGHIMPEDANCE tLZCE tPU VCC SUPPLY CURRENT 50% 50% ICC ISB DATA VALID HIGH IMPEDANCE tHZOE tPD tHZCE
Notes 19. The device is continuously selected. OE, CE = VIL, BHE, BLE, or both = VIL. 20. WE is HIGH for read cycle. 21. Address valid before or similar to CE, BHE, BLE transition LOW.
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Switching Waveforms (continued)
Figure 6. Write Cycle No 1: WE Controlled [22, 23, 24]
tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA
BHE/BLE
tBW
OE DATA I/O
NOTE 25
tSD DATAIN tHZOE
tHD
Figure 7. Write Cycle 2: CE Controlled [22, 23, 24]
tWC ADDRESS tSCE CE
tSA
WE
tAW tPWE
tHA
BHE/BLE
tBW
OE tSD DATA I/O
NOTE 25
tHD
DATAIN tHZOE
Notes 22. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals are ACTIVE to initiate a write and any of these signals terminate a write by going INACTIVE. The data input setup and hold timing are referenced to the edge of the signal that terminates the write. 23. Data I/O is high impedance if OE = VIH. 24. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state. 25. During this period, the I/Os are in output state. Do not apply input signals.
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Switching Waveforms (continued)
Figure 8. Write Cycle 3: WE Controlled, OE LOW [26]
tWC ADDRESS tSCE CE
BHE/BLE tAW WE tSA
tBW tHA tPWE
tSD DATA I/O
NOTE 27
tHD
DATAIN tHZWE tLZWE
Figure 9. Write Cycle 4: BHE/BLE Controlled, OE LOW [26]
tWC ADDRESS
CE tSCE
tAW tHA tBW tSA
BHE/BLE
WE
tHZWE
tPWE tSD DATAIN
tLZWE
tHD
DATA I/O
NOTE 27
Notes 26. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state. 27. During this period, the I/Os are in output state. Do not apply input signals.
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Truth Table
CE[28] H L L L L L L L L L L WE X X H H H H H H L L L OE X X L L L H H H X X X BHE X
[28]
BLE X
[28]
Inputs/Outputs High Z High Z Data out (I/O0-I/O15) Data out (I/O0-I/O7); I/O8-I/O15 in High-Z Data out (I/O8-I/O15); I/O0-I/O7 in High-Z High-Z High-Z High-Z Data in (I/O0-I/O15) Data in (I/O0-I/O7); I/O8-I/O15 in High-Z Data in (I/O8-I/O15); I/O0-I/O7 in High-Z
Mode Deselect/power-down Output disabled Read Read Read Output disabled Output disabled Output disabled Write Write Write
Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
H L H L L H L L H L
H L L H L L H L L H
Note 28. The `X' (Don't care) state for the Chip enable (CE) and Byte enables (BHE and BLE) in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted.
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Ordering Information
Speed (ns) 45 Ordering Code CY62136ESL-45ZSXI Package Diagram Package Type Operating Range Industrial 51-85087 44-Pin TSOP Type II (Pb-free)
Ordering Code Definition
CY 621 3 6 E SL 45 ZSX I
Temperature Grades I = Industrial ZSX = TSOP Type II (Pb-free) Speed Grade Wide Voltage Range (3 V and 5 V) E = Process Technology 90 nm Bus Width = x16 Density = 2 Mbit MoBL SRAM Family Company ID: CY = Cypress
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Package Diagram
Figure 10. 44-Pin TSOP II, 51-85087
PIN 1 I.D.
22
1
11.938 (0.470) 11.735 (0.462)
10.262 (0.404) 10.058 (0.396)
ZZZ ZXZ AA
23
44
TOP VIEW
BOTTOM VIEW
EJECTOR MARK (OPTIONAL) CAN BE LOCATED ANYWHERE IN THE BOTTOM PKG
0.800 BSC (0.0315)
0.400(0.016) 0.300 (0.012)
BASE PLANE 10.262 (0.404) 10.058 (0.396) 0.10 (.004)
18.517 (0.729) 18.313 (0.721) 0.150 (0.0059) 0.050 (0.0020) 1.194 (0.047) 0.991 (0.039) SEATING PLANE
0-5
0.210 (0.0083) 0.120 (0.0047)
0.597 (0.0235) 0.406 (0.0160)
DIMENSION IN MM (INCH) MAX MIN.
51-85087-*C
Acronyms
Acronym BHE BLE CMOS CE I/O OE SRAM TSOP VFBGA WE Description byte high enable byte low enable complementary metal oxide semiconductor chip enable input/output output enable static random access memory thin small outline package very fine ball gird array write enable
Document Conventions
Units of Measure
Symbol C A mA MHz ns pF V W Unit of Measure degrees Celsius microamperes milliampere megahertz nanoseconds picofarads volts ohms watts
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Document History Page
Document Title: CY62136ESL MoBL 2 Mbit (128K x 16) Static RAM Document Number: 001-48147 Rev. ** *A *B ECN No. 2615537 2718906 2944332 Orig. of Change VKN/PYRS VKN VKN Submission Date 12/03/08 06/15/2009 06/04/2010 Description of Change New Data Sheet Post to external web Added Contents Added footnote for ISB2 parameter in Electrical Characteristics Added Footnote 2 in Switching Characteristics Added footnote related to Chip enable and Byte enables in Truth Table Updated Package Diagram Updated links in Sales, Solutions, and Legal Information Updated datasheet as per new template Added Acronyms and Units of MeasureTable Added Ordering Code Definition Converted all tablenote to footnote.
*C
3126445
RAME
01/03/2011
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Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.
Products
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PSoC Solutions
psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5
(c) Cypress Semiconductor Corporation, 2008-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-48147 Rev. *C
Revised January 03, 2011
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MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
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